(1) Field of the Invention
The present invention relates generally to semiconductor integrated circuit technology and more particularly to nonvolatile memory devices such as flash EEPROMs (Electrically Erasable Programmable Read Only Memory).
(2) Description of Prior Art
Changes in time of the operating characteristics of a memory device are referred to as its endurance characteristics. Problem-free operation of a device for as long a period as possible should always be a basic requirement in its design and manufacture. Thus providing designs and manufacturing procedures leading to improved endurance characteristics are of fundamental importance.
The underlying concepts of the present invention can be succinctly stated. As a general rule, appropriate for flash memory cells, changes in operating characteristics occur with greater frequency at earlier times when larger potential differences exist or when potential differences exist over larger areas. Consequently, reducing potential differences, or reducing the area over which potential differences are applied can achieve improvements in endurance characteristics. These reductions should be implemented in such a way that other performance requirements are not impacted and so that there are minimal process and mask layout changes that are needed. The present invention provides a unique structure for a flash memory cell that allows for operation of the flash memory cell in a specified manner, which results in significantly improved endurance characteristics. The present invention also provides a method to fabricate such memory cells.
A traditional flash memory cell containing programming and reading channels and a method to fabricate such a traditional memory cell is shown in FIGS. 1a–4c. FIGS. 1a, 2a, 3a and 4a show top views depicting the progression of the process. FIGS. 1b, 2b, 3b and 4b show cross-sectional views depicting stages in forming a programming bit line channel and FIGS. 1c, 2c, 3c and 4c show cross-sectional views depicting stages in forming a reading bit line channel. Shown in FIGS. 1a, 1b and 1c are isolation regions, regions 4 and 52, such as shallow trench isolation (STI) regions, formed in a substrate, 6, which is usually a silicon substrate. Isolation regions 52 are unique to split programming and reading channel memory cells in which they serve to separate programming bit line channel regions, 54 and reading bit line regions, 56, of the memory cell. The area, 2, surrounding the isolation regions is the active area that will contain the memory cell devices. A gate insulator layer covering the active region, which for the sake of clarity is not explicitly shown in the figure, is usually a gate oxide layer. As shown in FIGS. 2a, 2b and 2c conductive floating gates, 8, are now formed, which are usually polysilicon floating gates. It is seen that a floating gate has a portion situated in the programming bit line channel region, 54 and a portion situated in the reading bit line channel region, 56 and a connecting portion that passes over the isolation region 52. An insulating layer that is required over the conductive gate is not explicitly shown and is usually formed by thermal oxidation. The positions for source regions, 10, are delineated at this stage and the source regions are now formed. Referring now to FIGS. 3a, 3b and 3c, conductive control gates, 12, are shown, which usually are polysilicon control gates. The conductive control gates being parallel conductive lines are appropriate for and are utilized as word lines. At this stage the positions of drain regions, 14, between adjacent control gates, are delineated and the drain regions are now readily formed. The next stage of the process is shown in FIGS. 4a, 4b and 4c. An overall insulator layer, 16, is then formed and conductive contact lines, 18 and 32, are disposed over the overall insulator layer, covering the programming bit line channels and the reading bit line channels, respectively and contacting drain regions, 14, through the overall insulator layer, 16. It is noted that the structures of the floating gates and control gates are the same in the programming bit line channels, FIGS. 3b and 4b and in the reading bit line channels, FIGS. 3c and 4c. 
As is well known, the array operation of flash memory devices is accomplished through three basic operations. In programming operations electrons are introduced into floating gates where they are stored. Erasing operations remove the stored charge from floating gates. Thus, there are two states, charged and uncharged, that floating gates could be in. Read operations are used to determine in which of the two states particular floating gates are in. This is accomplished utilizing the affect that a negatively charged floating gate causes an increase in the threshold voltage, which is the applied voltage required to obtain a conducting channel. Since the threshold voltage is larger for charged floating gates than for uncharged floating gates, applying a voltage intermediate between the threshold voltages will result in a conducting channel only for the uncharged floating gates. Therefore, the state of a floating gate is determined by the conduction state of the channel upon application of such an intermediate voltage.
For flash memory cells having distinct programming bit line channels and reading bit line channels, such as described above and in FIGS. 1a–4c, the programming operation mode is source side injection. In the source side programming operation mode electrons accelerated from a drain toward a source, in an electron channel induced under both the floating gate and control gate of a cell, are injected from the electron channel into the floating gate. Referring to FIG. 5a, source side injection is achieved for selected cells by the biasing scheme where the source potential, VSS, 22 of FIG. 5a, is about 10.5 volts, the control gate potential, VP2, 24 of FIG. 5a, is about 1.8 volts and the drain potential, VD, 20 of FIG. 5a, is set at VDP, which is defined as the drain potential to achieve 5 microamperes for VSS=10.5 volts and VP2=1.8 volts. This bias scheme is maintained for about 20 microseconds. For unselected cells, for which the floating gates are not to be charged, the bias scheme during programming differs only in that for unselected cells VD=VCC instead of VDP. In the erase operation, for which the erase mode is electron tunneling from the floating gates to the control gates, VD and VSS, 20 and 22 of FIG. 5a, are set to zero volts and the control gate potential, 24, VP2=12.5 volts. This erase operation bias scheme is maintained for about 2 milliseconds. In the reading operation the control gate potential VP2, 30 of FIG. 5b, is set at 2.5 volts, the source potential, VSS, 26 of FIG. 5b is set at zero volts and the drain potential, VD, 28 of FIG. 5b, is set at 1 volt. With this reading operation bias scheme channels under charged floating gates do not turn on and very little current is observed, while channels under uncharged floating gates readily turn on and consequently large currents are observed.
With these bias schemes the operation of traditional flash memory cells having distinct programming bit line channels and reading bit line channels, with structures such as described above and in FIGS. 1a–4c, would seem to be quite satisfactory. However, there are aspects of the structure and the bias scheme, as described above, which are detrimental to the endurance characteristics of the memory cells. The floating gate is a single conductive region that is contained within a cell, while the control gate, which acts as the word line, is a single conductive region that extends over all cells of a column. In addition, the shapes of the parts of the floating gate and control gate that are situated in the programming bit line channel, regions 8 and 12 of FIGS. 3b and 4b, are the same as the shapes of the parts of the floating gate and control gate that are situated in the reading bit line channel, regions 8 and 12 of FIGS. 3c and 4c. Therefore, potentials applied to the control gate during programming will stress regions in both the programming bit line portions and reading bit line portions of the cell. In the source side programming operation mode used, electrons are accelerated from a drain toward a source and an electron channel is required to be induced under both the floating gate and control gate of a cell. It is therefore necessary that the potentials VP2 and VD be applied on the control gate and drain to induce the channel and provide the acceleration. The application of these potentials cause the exertion of stress primarily over insulating layers separating the control and floating gates and the drain from conductive regions at different potentials. This is the case for all regions of the floating and control gates, even those that are situated in the reading bit line channel. Over long term operation of the cell this could lead to degradation in the properties of the stressed insulating layers, which could, for instance, become leaky or could even suffer catastrophic breakdown. Another disadvantage of the traditional structure and bias scheme is the high source potential VSS=10.5 volts that is required to be applied. Such a high potential could more readily induce such detrimental effects as reverse tunneling, punch-through and excessive leakage current. Thus, there are significant disadvantages inherent in the traditional structure and bias scheme stemming from their reduced endurance characteristics.
Li et al. U.S. Pat. No. 6,255,169 B1 discloses a process for fabricating a high-endurance non-volatile memory device. The process includes the step of forming a nitrogen region in a semiconductor substrate prior to carrying out a thermal oxidation process. U.S. Pat. No. 5,648,669 to Sethi et al. shows a high speed flash memory cell.